Multiplexer circuits are very common in integrated circuits (ICs) and other electronic circuits. For example, multiplexer circuits are used throughout many programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs), to programmably select one of several different input signals to pass to a logic destination, or to select one of several stored values to provide as the output signal from a lookup table (LUT). Therefore, multiplexers can form a significant portion of the logic circuitry in a PLD. Hence, reducing the power dissipation and/or the leakage current of these multiplexers can significantly improve the overall performance of an electronic device in these increasingly important areas.
FIG. 1 illustrates a well known 8-to-1 binary multiplexer circuit. A similar multiplexer circuit is commonly included in FPGA LUTs, for example, although LUTs typically have 16 input signals. The choice of eight input signals for the various multiplexer circuits illustrated herein is purely exemplary. Multiplexer circuits often have fewer or more than eight input signals. The drawings herein are standardized on 8-to-1 multiplexer circuits simply to simplify the drawings and to provide a common standard for comparison purposes. Multiplexer circuits having different numbers of input signals are easily extrapolated from the illustrated examples by those of skill in the relevant arts.
The circuit of FIG. 1 includes 8 input terminals IN0–IN7, three select terminals S0–S2, an output terminal OUT, N-channel transistors 100–107, 110–113, and 120–121, inverters 141–143, and half-latch 130. Half-latch 130 includes inverter 131 and pullup 132. (In the present specification, the same reference characters are used to refer to terminals, signal lines, signal nodes, and their corresponding signals.)
A high value on select signal S0 passes signals IN7, IN5, IN3, and IN1 to internal nodes INT3, INT2, INT1, and INT0, respectively. A low value on select signal S0 is inverted by inverter 141 to provide a high signal that passes signals IN6, IN4, IN2, and IN0 to internal nodes INT3, INT2, INT1, and INT0, respectively. A high value on select signal S1 passes signals INT3 and INT1 to internal nodes INT5 and IN4, respectively. A low value on select signal S1 is inverted by inverter 142 to provide a high signal that passes signals INT2 and INT0 to internal nodes INT5 and INT4, respectively. A high value on select signal S2 passes signal INT5 to internal node INT6. A low value on select signal S2 is inverted by inverter 143 to provide a high signal that passes signal INT4 to internal node INT6.
A low value on internal node INT6 is inverted by inverter 131 and provides a high value (power high VDD) at the output terminal OUT. However, an N-channel transistor passes a high value with a voltage drop of one N-channel threshold voltage Vth from the gate voltage. Therefore, a high value passed to node INT6 equals not power high VDD, but VDD-Vth. At today's low operating voltages, this reduced high value may not fully turn off the pullup, or turn on the pulldown, included in inverter 131. Therefore, pullup 132 is provided on internal node INT6 to pull the node fully to VDD whenever output terminal OUT reaches a sufficiently low value to turn on the pullup. Thus, inverter 131 functions properly and leakage through the inverter is reduced.
The circuit of FIG. 1 works well with sufficiently high values of VDD. As long as the voltage level VDD-Vth is high enough to flip inverter 131 and turn on pullup 132, the circuit functions properly. However, power high voltage levels (VDD) are much lower in today's ICs than was previously the case. For example, when VDD=1.2 volts and Vth=0.5 volts, a voltage level of VDD−Vth=0.7 volts cannot be relied upon to flip inverter 131.
Various methods have been used to resolve this problem. One known method is to use a gate voltage higher than VDD when driving a high value onto the gates of N-channel transistors 100–107, 110–113, and 120–121 (i.e., signals S0–S2 and inverters 141–143 are implemented using a “pumped” power high voltage greater than VDD). For example, if the gate voltage is higher than VDD by one threshold voltage Vth, the resulting voltage at node INT6 is (VDD+Vth−Vth), or simply VDD. Another approach is to lower the threshold voltage of N-channel transistors 100–107, 110–113, and 120–121. However, each of these solutions complicates the fabrication of the circuit, especially at very short gate lengths. These solutions are becoming less viable as IC gate lengths become shorter and shorter, and VDD values lower and lower, with the passage of time.
An alternative solution to this problem is presented in FIG. 2. As previously described, an N-channel transistor passes only a “degraded” (e.g., reduced) version of a high voltage value. However, a P-channel transistor passes high voltage values with no voltage degradation. Therefore, the voltage degradation can be eliminated by replacing the N-channel transistors with CMOS passgates, each of which includes a pair of N-channel and P-channel transistors coupled in parallel. The P-channel transistor is gated by the inverse signal of the associated N-channel transistor. The N-channel transistor provides a fast response to a high input signal, while the P-channel transistor pulls a high output value fully “to the rail”, i.e., all the way to VDD.
The multiplexer circuit of FIG. 2 is similar to the circuit of FIG. 1, except that N-channel transistors 100–107, 110–113, and 120–121 are replaced by CMOS pass transistors 200–207, 210–213, and 220–221. The N-channel transistors are gated by the same signals as in FIG. 1, and the P-channel transistors are gated by the inverted signals. Components unchanged from those of FIG. 1 are similarly numbered, and are not again described.
Note that the pullup 132 of FIG. 1 is not needed in the circuit of FIG. 2, because a high value provided to node INT6 already has the full value of VDD.
However, the circuit of FIG. 2 also has its drawbacks. For example, a matrix of passgates that includes both N-channel and P-channel transistors (as in the circuit of FIG. 2) requires more than twice as much area to implement within an IC. This limitation is partially due to the fact that P-channel transistors are placed within an N-well in the substrate. The N-well consumes additional area, both in itself and in the extra spacing required to isolate the N-well from the N-channel transistors. Additionally, a P-channel transistor must be made about twice as wide as an N-channel transistor to provide the same speed of operation. Therefore, each P-channel transistor consumes much more area than the associated N-channel transistor.
Therefore, it is desirable to provide multiplexer circuits and methods that pass a full high value (i.e., VDD) to the circuit output node, but do not unduly complicate the fabrication process, and which consume less area than the CMOS solution illustrated in FIG. 2.